veryllang/veryl repository overview

⁠Veryl Hardware Description Language

Veryl is a hardware description language alternate to SystemVerilog, providing the following advantages:

• Optimized syntax for synthesizable RTL
• Interoperability with SystemVerilog
• Productivity tools by default

To get more information, please check the following links.

• Web site⁠
• Language Reference⁠
• GitHub⁠
• Discord⁠

⁠Tags

Tags indicate Veryl versions, base images, and flavors. The following examples are tags provided for Veryl 0.16.4.

• Latest: latest
• Debian: trixie, bookworm, bullseye
• Debian(slim): slim-trixie, slim-bookworm, slim-bullseye
• Alpine: alpine, alpine3.22, alpine3.21, alpine3.20
• Version: 0.16, 0.16.4
• Version with base images: 0.16-trixie, 0.16.4-trixie, ...

⁠Getting started

⁠Pull the latest image

$ docker pull veryllang/veryl

⁠Build a Veryl project

$ docker run --rm -v `pwd`:/work -w /work veryllang/veryl veryl build